;*******************************************************************************
;Copyright © hanghai Awinic Technology Co., Ltd. 2019 2019 . All rights reserved.
; Description: starip file
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size      EQU     0x00000800 ;0x00000100 256Byte 0x00000400   1k

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp


; <h> Heap Configuration
;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size       EQU     0x00000000 ;0x00000100 256Byte 0x00000200  512Byte

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit

                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset
                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors
                EXPORT  __Vectors_End
                EXPORT  __Vectors_Size

__Vectors       DCD     __initial_sp                   ; Top of Stack
                DCD     Reset_Handler                  ; Reset Handler
                DCD     NMI_Handler                    ; NMI Handler
                DCD     HardFault_Handler              ; Hard Fault Handler
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     SVC_Handler                    ; SVCall Handler
                DCD     0                              ; Reserved
                DCD     0                              ; Reserved
                DCD     PendSV_Handler                 ; PendSV Handler
                DCD     SysTick_Handler                ; SysTick Handler

                ; External Interrupts
                DCD     RPL_IRQnHandler                ; Undervoltage /high voltage /ripple
                DCD     TIMER0_IRQnHandler             ; Timer 0 Interrupt
                DCD     TIMER1_IRQnHandler             ; Timer 1 Interrupt
                DCD     UART0_IRQnHandler              ; UART0 Interrupt
                DCD     IIC0_IRQnHandler               ; IIC0 Interrupts
                DCD     AFE0_IRQnHandler               ; AFE0 Interrupts
                DCD     AFE_CMP0_IRQnHandler           ; AFE CMP0 Interrupts
                DCD     AFE_CMP1_IRQnHandler           ; AFE CMP1 Interrupts
                DCD     PA_IRQnHandler                 ; PA interruption except 2 to 4
                DCD     RMC_IRQnHandler                ; RAM parity interrupt
                DCD     RFC_IRQnHandler                ; Flash controller interrupt
                DCD     WDt0_IRQnHandler               ; Watchdog
                DCD     SWDt_IRQnHandler               ; smart Watchdog
                DCD     WDt1_IRQnHandler               ; Watchdog

__Vectors_End

__Vectors_Size  EQU  __Vectors_End - __Vectors

                AREA    |.text|, CODE, READONLY

; Reset handler routine
Reset_Handler    PROC
                 EXPORT  Reset_Handler                 [WEAK]
        IMPORT  __main
        ;IMPORT  aw_m0_system_init
                 ;LDR     R0, =aw_m0_system_init
                 ;BLX     R0
                 LDR     R0, =__main
                 BX      R0
                 ENDP

; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler     PROC
                EXPORT  NMI_Handler                    [WEAK]
                B       .
                ENDP
HardFault_Handler\
                PROC
                EXPORT  HardFault_Handler              [WEAK]
                B       .
                ENDP
SVC_Handler     PROC
                EXPORT  SVC_Handler                    [WEAK]
                B       .
                ENDP
PendSV_Handler  PROC
                EXPORT  PendSV_Handler                 [WEAK]
                B       .
                ENDP
SysTick_Handler PROC
                EXPORT  SysTick_Handler                [WEAK]
                B       .
                ENDP

Default_Handler PROC

                EXPORT  RPL_IRQnHandler            [WEAK]
                EXPORT  TIMER0_IRQnHandler         [WEAK]
                EXPORT  TIMER1_IRQnHandler         [WEAK]
                EXPORT  UART0_IRQnHandler          [WEAK]
                EXPORT  IIC0_IRQnHandler           [WEAK]
                EXPORT  AFE0_IRQnHandler           [WEAK]
                EXPORT  AFE_CMP0_IRQnHandler       [WEAK]
                EXPORT  AFE_CMP1_IRQnHandler       [WEAK]
                EXPORT  PA_IRQnHandler             [WEAK]
                EXPORT  RMC_IRQnHandler            [WEAK]
                EXPORT  RFC_IRQnHandler            [WEAK]
                EXPORT  WDt0_IRQnHandler           [WEAK]
                EXPORT  SWDt_IRQnHandler           [WEAK]
                EXPORT  WDt1_IRQnHandler           [WEAK]
RPL_IRQnHandler
TIMER0_IRQnHandler
TIMER1_IRQnHandler
UART0_IRQnHandler
IIC0_IRQnHandler
AFE0_IRQnHandler
AFE_CMP0_IRQnHandler
AFE_CMP1_IRQnHandler
PA_IRQnHandler
RMC_IRQnHandler
RFC_IRQnHandler
WDt0_IRQnHandler
SWDt_IRQnHandler
WDt1_IRQnHandler
                B       .

                ENDP

                ALIGN

;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
                 IF      :DEF:__MICROLIB

                 EXPORT  __initial_sp
                 EXPORT  __heap_base
                 EXPORT  __heap_limit

                 ELSE

                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap

__user_initial_stackheap

                 LDR     R0, =  Heap_Mem
                 LDR     R1, =(Stack_Mem + Stack_Size)
                 LDR     R2, = (Heap_Mem +  Heap_Size)
                 LDR     R3, = Stack_Mem
                 BX      LR

                 ALIGN

                 ENDIF

                 END
